The present invention relates generally to delta-sigma modulator based fractional-N phase locked loop frequency synthesizers and deals more particularly with a delta-sigma modulator based fractional-N phase locked loop frequency synthesizer with a sine wave generator to break the periodicity of the delta-sigma modulator output to eliminate the generation of fractional spurious frequencies.
Digital frequency synthesizers have long been used in communication systems, particularly RF communication systems, to generate RF signals carried over RF channels. In frequency synthesis, it is desirable to achieve the selected frequency output in as little time as possible with any spurious outputs minimized. It is known to create a frequency synthesizer by placing a frequency divider function between the voltage-controlled oscillator (VCO) output and the phase frequency detector (PFD) in a phase-locked loop (PLL), wherein the output is an integer-N multiple of the input reference frequency to the PFD. The spurious outputs in question are usually associated with phase detectors and occur at the phase detector operating frequency, which is generally the same as the channel spacing. Incorporating a fractional-N division function in the PLL helps overcome problems of spurious frequency outputs in an integer PLL by allowing the phase detector to operate at a much higher frequency for the same channel spacing.
A number of methods that are based upon the concept of integer-N frequency synthesis are known to realize the fractional-N division function and include pulse swallowing, phase interpolation, Wheatly random jittering and deltasigma modulation to control the multi-modulus, including dual-modulus, frequency dividers to provide the division function. Of the known methods, a delta-sigma modulator realization of a fractional-N frequency synthesizer is desirable and preferable to achieve low phase noise, fast settling time, fine channel resolution and wide tuning bandwidth. The delta-sigma modulator fractional-N phase locked loop frequency synthesizer is based on the concept of division ratio averaging, wherein an integer frequency divider rather than a fractional frequency divider is used, and the division ratio is dynamically switched between two or more values, effectively providing a non-integer number division function. One of the more important advantages of using the delta-sigma modulator to control a multi-modulus is the ability to shape phase noise introduced by the delta-sigma modulator controlled fractional-N division function. A problem generally associated with such a deltasigma modulator fractional-N frequency synthesizer is the appearance or presence of fractional spurious levels at a fractional offset frequency. The fractional spurious levels may also appear at the fractional offset frequency harmonics. The fractional spurious levels in delta-sigma modulator based fractional-N frequency synthesizers may originate from several sources including the operation of the delta-sigma modulator itself, coupling between the multi-modulus prescaler or charge pump driving the loop filter and the outside world through power supply feeds or substrates, and the nonlinearity of the charge pump. The fractional spurious frequencies may also originate from the spacing error or timing error of the multimodulus prescaler.
It is a general object therefore of the present invention to provide a method and related apparatus to prevent the generation of spurious frequency errors in a delta-sigma based fractional-N frequency synthesizer.
It is another object of the present invention to break the periodicity of the multi-modulus control output signal of the delta-sigma modulator to eliminate fractional spurious frequencies in the fractional-N frequency synthesizer originating from the operation of the delta-sigma modulator.
It is a further object of the present invention to provide a delta-sigma based fractional-N phase locked loop frequency synthesizer with a sine wave generator to break the periodicity of the output signal of the delta-sigma modulator to eliminate the production of fractional spurious frequencies.
Other objects and features of the present invention will become readily apparent from the following written detailed description taken together with the drawings forming a part thereof.
The invention resides in a fractional-N frequency synthesizer having a delta-sigma modulator control of the division ratio of a multi-modulus frequency divider in the feedback path of the phase locked loop. The output control signal of the delta-sigma modulator is dithered to break the periodicity of the division ratio control signal which occurs when the fractional control input words to the delta-sigma modulation has too few xe2x80x9czerosxe2x80x9d or xe2x80x9conesxe2x80x9d which cause the generation of fractional spurious frequencies. The invention avoids the generation of the fractional spurious frequencies.
In a one aspect of the invention, a delta-sigma fractional-N frequency synthesizer comprises a phase locked loop including a phase frequency detector, a loop filter, a voltage-controlled oscillator and a multi-modulus frequency divider in a feedback loop between the voltage-controlled oscillator output and an input of the phase frequency detector. The delta-sigma modulator has an input for receiving a fractional control word and an output coupled to the multi-modulus frequency divider for controlling the division ratio of the multi-modulus frequency divider in response to the input fractional control word. A generator produces a signal in accordance with and related to a frequency compensation loop error signal from the multi-modulus frequency divider. Means are provided for adding the generator signal output to the fractional input control word to produce a zero average dither fractional control word as the input to the delta-sigma modulator. The delta sigma modulator generates a multi-modulus input control signal whereby the division ratio is changed without generation of fractional spurious frequencies.
Preferably, the order of the delta-sigma modulator has an integer value in the range of Z to X, where Z is an integer value of at least 2 and X has an arbitrary integer value greater than Z.
Preferably, the generator output signal frequency has a value in the range of Fcomp/Z to Fcomp/Y, where Z is an integer value of at least 2 and the maximum value of Y is related to the loop filter and the frequency compensation loop error signal.
Preferably, the generator signal output is an asymmetrical signal.
Preferably, the generator signal output is a symmetrical signal.
Preferably, the generator is a symmetrical sine wave generator.
Preferably, the generator is an asymmetrical sine wave generator.
Preferably, Fcomp/Z is equal to 4.
Preferably, Fcomp/Z is equal to 8.
Preferably, Fcomp/Z is equal to 16.
Preferably, Fcomp/Z has an arbitrary integer value equal to or greater than 1.
Preferably, the multi-modulus frequency divider is a dual-modulus frequency divider.
In a further aspect of the invention, the dual-modulus frequency divider includes a prescaler coupled to the output of the voltage-controlled oscillator and includes an N-divider and A-divider coupled to the output of the prescaler. The prescaler has a division ratio control input coupled to the A-divider to switch the division ratio in response to the A-divider completing a predetermined count.
In another aspect of the invention, the fractional input control word further comprises a separate Finput control signal and an Minput control signal. Means are provided for combining the Finput control signal and the generator signal output to produce a delta-sigma modulator input control word. The delta-sigma modulator generates an output control word in response to the input control word. Means are also provided for combining the Minput control signal and the delta-sigma modulator output control word to generate the multi-modulus frequency divider division ratio control.
Preferably, the multi-modulus frequency divider further comprises a dual multi-modulus frequency divider.
In a further aspect of the invention, the fractional input control word further comprises a separate Finput control signal and an Ainput control signal and an Ninput control signal. Means are provided for combining the Finput control signal and the generator signal output to produce a delta-sigma modulator input control word. The delta-sigma modulator generates an output control word in response to the input control word. Means are provided for combining the Ainput control signal and the delta-sigma modulator output control word to generate a multi-modulus xe2x80x9cAxe2x80x9dcontrol input signal. Means are also provided for combining the Ninput control signal and the result of the combined Ainput control signal and delta-sigma modulator output control word to generate a multi-modulus xe2x80x9cNxe2x80x9d control input signal.